The present invention relates to a semiconductor device and, in particular, a semiconductor memory device having field effect transistors formed by polycrystalline silicon films.
A MIS transistor (e.g., a metal insulator semiconductor transistor or an insulated gate field effect transistor) using a polycrystalline silicon film which is formed above the surface of the semiconductor substrate is a transistor most suited to a high density integrated circuit device. FIG. 7 shows the sectional view of such a conventional transistor. The MIS transistor is composed of: a first polycrystalline silicon film for forming a source region 3a on a silicon oxide film (SiO.sub.2 film) 2 which, in turn, is on a silicon substrate 1, a channel region 3', and a drain region 3b; a gate insulating film 4 formed on the above referred-to polycrystalline silicon film; and a gate electrode 5 comprising a second polycrystalline silicon film formed on the gate insulating film 4.
In a device of this type, the gate electrode 5 is used as an ion implantation mask, i.e. ions of impurity atoms, such as boron or others, are implanted in the source region 3a and the drain region 3b, and the channel region 3' of the MIS transistor is formed in a self-alignment manner. When the source region, drain region, and channel region are not formed in the self-alignment manner with the gate electrode, the source region, the drain region, and the channel region are formed by limiting the impurity atom ion implantation region using a photoresist or other scheme as an ion implantation mask. The gate electrode is placed above or under the channel region.
A device of this type is described in IEDM. Tech. Dig., December 1983, pp. 202-205.
A semiconductor device having a conventional static random access memory cell has been implemented using the above field effect transistor, which is formed by a polycrystalline silicon film to form a driver transistor, a load transistor, or a transfer transistor. An example of such a semiconductor memory device is disclosed in Japanese Patent Laid-Open 2-14564.
In the above conventional MIS transistor using polycrystalline silicon, the trap level is formed on the grain boundary of the polycrystalline silicon, carriers are trapped on this trap level, and potential barriers are formed. Therefore, it is difficult to control the threshold voltage of the MIS transistor. It is determined that a leakage current flowing between the source and drain regions when the MIS transistor is cut off is caused by a recombination current in a depletion layer which is formed on the above trap level by trapped carriers. This leakage current causes a problem that when the MIS transistor using a polycrystalline silicon film is applied to, for example, a static random access memory cell, the standby power consumption increase extremely.
Furthermore, the experimental study of the inventors of the present invention shows that when ions are implanted in the channel region by the same means as that of the well-known MOS (metal oxide semiconductor) formed on the substrate so as to control the threshold voltage of a MIS transistor having a large amount of such a trap level, there is a phenomenon found that the leakage current between the source and drain regions, which is caused by the electric field at the end of the channel region on the drain region side, increases. This trend grows as the implantation dose in the channel region increases as shown in FIG. 3.
Japanese Patent Laid-Open 62-98665 indicates that an impurity is used as a high resistance load element so as to increase the threshold voltage of a parasitic MISFET.